The present invention relates, in general, to electronics and, more particularly, to semiconductor device structures and methods of forming semiconductor devices.
Gallium Nitride High Electron Mobility Transistors (GaN HEMTs), or generally III-nitride HEMTs, GaN Field Effect Transistors (FETs), or III-nitride transistors (and even more generally group III-V transistors), are known semiconductor devices and have experienced increased usage because of their high breakdown voltage and high switching speeds. Various applications have used group III-V transistors together with silicon diodes to provide, for example, a clamp structure to protect the group III-V transistor from electrical overstress. For example, some applications have used the silicon diode configured in parallel with the group III-V transistor with the anode connected to the source region of the group III-V transistor and the cathode connected to the drain region of the group III-V transistor.
Although group III-V transistors have been configured to operate as depletion mode devices (i.e., normally-on) or to operate as enhancement mode devices (i.e., normally-off), depletion mode devices have been easier to fabricate. One approach in providing a normally-off group III-V transistor has been to combine a normally-on group III-V transistor in a cascode configuration with a normally-off silicon metal oxide semiconductor FET (MOSFET). In such a configuration, the normally-off silicon MOSFET has been connected to the normally-on group III-V transistor in series (i.e., source of group III-V transistor connected to the drain of the silicon MOSFET) with the gate of the group III-V transistor connected to the source of the silicon MOSFET.
Unclamped inductive switching (“UIS”) capability is one factor that determines the ruggedness of power semiconductor devices including group III-V transistors. UIS is one important parameter in certain applications involving an inductive load. During switching operations, the inductor can force a high voltage and high current condition, which can cause a high electrical stress on the power semiconductor device. In silicon semiconductor devices, because of the presence of an internal diode, the avalanche capability of such devices helps the device clamp the voltage and supply the necessary current before the energy is sent to ground. However, in the case of group III-V transistor devices, avalanche capability does not exist due to the absence of an internal diode. Thus, the reverse current will force an increase in the voltage at the drain of the device under UIS condition and eventually weaken or destroy the device. This problem further exists with cascode configurations because, among other things, the group III-V transistor has been placed between the load and the silicon MOSFET device and the internal diode of the silicon MOSFET cannot provide protection for the group III-V transistor.
Accordingly, structures and methods of integrating and/or making such structures are needed to improve the ruggedness of heterojunction power devices, such as group III-V transistor devices. It would be beneficial for such structures and methods to be cost effective and efficient for manufacturing integration, and to not detrimentally affect device performance.
For simplicity and clarity of the illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein, current-carrying electrode means an element of a device that carries current through the device, such as a source or a drain of an MOS transistor, an emitter or a collector of a bipolar transistor, or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device, such as a gate of a MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-type regions and certain P-type regions, a person of ordinary skill in the art understands that the conductivity types can be reversed and are also possible in accordance with the present description. Also, the devices explained herein can be Ga-face GaN devices or N-face GaN devices. One of ordinary skill in the art understands that the conductivity type refers to the mechanism through which conduction occurs such as through conduction of holes or electrons, therefore, and that conductivity type does not refer to the doping concentration but the doping type, such as P-type or N-type. It will be appreciated by those skilled in the art that the words during, while, and when as used herein relating to circuit operation are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay(s), such as various propagation delays, between the reaction that is initiated by the initial action. Additionally, the term while means that a certain action occurs at least within some portion of a duration of the initiating action. The use of the word approximately or substantially means that a value of an element has a parameter that is expected to be close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to at least ten percent (10%) (and up to twenty percent (20%) for semiconductor doping concentrations) are reasonable variances from the ideal goal of exactly as described. The terms first, second, third and the like in the claims or/and in the Detailed Description of the Drawings, as used in a portion of a name of an element are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments described herein are capable of operation in other sequences than described or illustrated herein. For clarity of the drawings, doped regions of device structures are illustrated as having generally straight line edges and precise angular corners. However, those skilled in the art understand that due to the diffusion and activation of dopants the edges of doped regions generally may not be straight lines and the corners may not be precise angles. Additionally, it is to be understood that where it is stated herein that one layer or region is formed on or disposed on a second layer or another region, the first layer may be formed or disposed directly on the second layer or there may be intervening layers between the first layer and the second layer. Further, as used herein, the term formed on is used with the same meaning as located on or disposed on and is not meant to be limiting regarding any particular fabrication process. Moreover, the term “major surface” when used in conjunction with a semiconductor region, wafer, or substrate means the surface of the semiconductor region, wafer, or substrate that forms an interface with another material, such as a dielectric, an insulator, a conductor, or a polycrystalline semiconductor. The major surface can have a topography that changes in the x, y and z directions. Additionally, the term integrated as used in herein generally means that described elements are incorporated within, partially within, and/or on a common semiconductor region or body.